1. Field of the Invention
The present invention relates to a micro controller unit (MCU) and more particularly to generation and control of a clock signal defining an operation thereof.
2. Description of the Background Art
In general, a conventional micro controller unit (which will be hereinafter referred to as an “MCU”) is wholly operated based on a single clock. With a requirement for an increase in a speed of the MCU, recently, a frequency of the clock has been increased. However, in the case in which a block (a high-speed block) which can correspond to a clock having a high frequency and a block (a low-speed block) which cannot correspond thereto are present in the MCU to be operated based on the single clock, for example, the frequency of the clock to be used in the MCU is to be set within a range to which the low-speed block can correspond. For this reason, the speed of the whole MCU cannot be increased. More specifically, an operation speed of the high-speed block which can originally be operated at a high speed is determined by that of the low-speed block. In order to increase the speed of the MCU, moreover, there is also a problem in that the low-speed block is to be redesigned greatly.
On the other hand, there has also been proposed an MCU in which a frequency of a clock for a central processing unit (CPU) (a CPU clock) and a frequency of a clock for a peripheral circuit (a peripheral clock) can be set optionally (for example, Japanese Patent application Laid-Open No. 11-272644 (1999) (pages 1 to 7, FIGS. 1 to 5) (which will be hereinafter referred to as “Patent Document 1”).
In the conventional MCU disclosed in the Patent Document 1, the frequencies of the CPU clock and the peripheral clock can be set optionally. In some cases, however, phases of the CPU clock and the peripheral clock are not coincident with each other. It is necessary to provide, in the MCU, a circuit (for example, a latch circuit) for synchronizing both operations when the CPU accesses the peripheral circuit or the like. Thus, there is a fear of complexity of a circuit structure of the MCU and an increase in a cost.
There is also an MCU for generating a CPU clock from a peripheral clock which has been disclosed in FIG. 5 of the Patent Document 1. In such an MCU, the CPU clock having a different frequency from that of the peripheral clock is generated by leaving a space between pulses of the peripheral clock. In this case, a synchronization of operations of the CPU and the peripheral circuit is maintained. Therefore, there is not the problem described above.
In the case in which the high-speed block and the low-speed block are present in the MCU, however, the peripheral clock cannot but be set to have a frequency within a range to which the low-speed block can correspond. As a result, a frequency of the CPU clock generated from the peripheral clock is determined by that of the peripheral clock so that a performance of the CPU capable of originally carrying out a high-speed operation cannot be fully exhibited. In recent years in which the speed of the operation of the CPU can be increased, this problem has been great. As a countermeasure, it is preferable that a peripheral circuit capable of carrying out a high-speed operation should be used in an MCU mounting a high-speed CPU. In that case, a cost of the MCU is increased.
Moreover, there is a problem in that power consumption of the whole MCU is generally increased when the clock frequency of the MCU is increased. In a device for carrying out battery driving, for example, a portable terminal device or a notebook computer, particularly, a reduction in the power consumption is an important problem.